1. Field of the Invention
The present invention relates to a digital signal decoding device and digital signal decoding method, which are applied to a digital signal reproduction apparatus such as an optical disk apparatus or the like and, more particularly, to a digital signal decoding device and digital signal decoding method, which are applied to a signal reproduction circuit that exploits a PRML technique.
2. Description of the Related Art
As recording media that can record and reproduce digital data, optical disks represented by DVDs (Digital Versatile Disks) are known. A DVD-RAM as one of DVDs comprises a signal recording layer. When this recording layer is irradiated with a laser beam having appropriate energy, its crystal state changes. When the recording layer is irradiated with a laser beam of appropriate energy again, reflected light is obtained in a quantity corresponding to the crystal state of the recording layer. By detecting this reflected light, digital data recorded on the recording layer can be reproduced.
In recent years, a PRML technique is adopted to improve the recording density. Jpn. Pat. Appln. KOKAI Publication No. 9-17130 (reference 1) discloses the PRML technique. The contents of that technique will be briefly explained below.
Partial Response (PR) is a method of reproducing data while compressing a required signal band by positively utilizing intersymbol interference (interference between reproduction signals corresponding to bits which are recorded at neighboring positions). PR can be further categorized into a plurality of different classes depending on the way intersymbol interference is produced at that time. For example, in case of class 1, recorded data “1” is reproduced as 2-bit reproduction data “11”, and intersymbol interference is produced for the subsequent 1 bit. A Viterbi decoding method (ML) is a kind of so-called maximum likelihood sequence estimation methods, and reproduces data on the basis of information of signal amplitudes at a plurality of times by effectively using the intersymbol interference rules of a reproduction waveform. For this process, synchronous clocks, which are synchronized with a reproduction waveform obtained from a recording medium, are generated, and the reproduction waveform itself is sampled using the clocks to be converted into amplitude information. After that, the amplitude information undergoes appropriate waveform equalization to be converted into a predetermined PR response waveform. A Viterbi decoder then outputs a maximum likely data sequence as reproduction data using old and current sample data. A combination of the aforementioned PR method and Viterbi decoding method (most likelihood decoding) is called a PRML method. PR can calculate a reproduction signal sequence by a convolution operation of an impulse response of a predetermined PR class with respect to a recorded data sequence. In other words, PR can express a process from recording to reproduction as an arbitrary finite state machine having N states (N=2m−1 where m is the response length of the predetermined PR). A two-dimensional graph that expresses (N) states at arbitrary time k of this finite state machine as nodes which line up in the vertical direction, and expresses transition from the respective states to those at time (k+1) as branches is called a trellis diagram. A Viterbi algorithm is used to obtain a recorded signal sequence from a reproduction signal sequence, i.e., to find the shortest path on this trellis diagram, and is equivalent to a dynamic programming problem with respect to a multistage decision process. A Viterbi decoder based on this algorithm is used to make most likelihood estimation of a transmission sequence in band-limited channels having intersymbol interference. That is, a code sequence that minimizes a distance metric (distance function) associated with a sequence of reception signals such as the sum total of square errors of the sequence of reception signals or the like is selected from possible code sequences. In order to put this PRML technique into practice, a high-precision adaptive equalization technique that obtains a reproduction signal as a response of a predetermined PR class, and a high-precision clock reproduction technique that supports the former technique are required.
A runlength limited code used in the PRML technique will be explained below. A PRML reproduction circuit generates clocks synchronized with a signal itself reproduced from a recording medium. In order to generate stable clocks, the polarity of a recorded signal must be inverted within a predetermined period of time. At the same time, the polarity of the recorded signal must be inhibited from being inverted during the predetermined period of time, so as to reduce the maximum frequency of the recorded signal. A maximum data length free from inversion of the polarity of the recorded signal is called a maximum runlength, and a minimum data length free from inversion of the polarity is called a minimum runlength. A modulation rule which has a maximum runlength of 8 bits and a minimum runlength of 2 bits is called (1, 7)RLL. Also, a modulation rule which has a maximum runlength of 8 bits and a minimum runlength of 3 bits is called (2, 7)RLL. As a typical modulation/demodulation method used in an optical disk, (1, 7)RLL and EFM Plus are known, and are disclosed in U.S. Pat. No. 5,696,505 (reference 2).
In recent years, the data reproduction speed of an optical disk apparatus and the like is increasing rapidly, and an operation speed of 500 MHz or higher is required. The consumption power of the data reproduction circuit increases in proportion to the operation speed. Also, an increase in recording linear density requires a PRML signal process of higher orders. Use of PRML of higher orders requires more complicated signal processes, and a larger-scale circuit. However, an optical disk apparatus with low consumption power is demanded due to prevalence of notebook type PCs, and the consumption power of a PRML reproduction circuit must be considerably reduced. Furthermore, a Viterbi decoder as a part of the PRML reproduction circuit bottlenecks an increase in processing speed since it executes feedback loop processes called ACS processes in addition to its complicated circuit.
In order to solve these problems, a technique that can simplify the circuit of a Viterbi decoder is disclosed in Jpn. Pat. No. 2,755,375 (reference 3). Furthermore, a technique that can improve the operation speed while suppressing an increase in circuit scale by adding a preload process called Radix-4 to the technique disclosed in this reference 3 is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-22840 (reference 4). Furthermore, a technique that can improve the operation speed of a Viterbi decoder is disclosed in “A New architecture for the fast Viterbi algorithm”, Inkyu Lee, Sonntag, J. L., Global Telecommunications Conference, 2000, GLOBECOM '00. IEEE, Volume: 3, 2000, pp. 1664-1668 (reference 5).
According to the technique disclosed in reference 3, a circuit can be simpler than a Viterbi decoder using the general Viterbi algorithm, but the operation speed cannot be improved.
According to the technique disclosed in reference 4, the preload process results in an increase in operation word length, and increases the consumption power beyond the improved processing speed.
Furthermore, according to the technique disclosed in reference 5, add and compare processes unique to the Viterbi algorithm can be parallelly executed, and the operation speed can be improved. However, the circuit complexity increases considerably due to the parallel processes, resulting in an increase in consumption power.